1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device and, more particularly, to a semiconductor memory device including a word line driver circuit for driving word lines.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a known word line driver circuit.
Referring to FIG. 1, the word line driver circuit includes first to fourth word line drivers 110 to 140. The word line driver circuit includes a PMOS transistor region 150 including first to fourth PMOS transistors P1 to P4.
The first word line driver 110 includes the first PMOS transistor P1 for pulling up a first word line signal WL1 to a level of a first sub-word line selection signal FX1 in response to a main word line signal MWLB, an NMOS transistor N1_1 for pulling down the first word line signal WL1 to a ground voltage level in response to the main word line signal MWLB, and an NMOS transistor N1_2 for pulling down the first word line signal WL1 to the ground voltage level in response to a first inverse sub-word line selection signal FXB1. The main word line signal MWLB is a memory cell driving signal transferred through a main word line. The first word line signal WL1 is a signal for driving a sub-word line. The first sub-word line selection signal FX1 is a signal having a specific voltage level based on address information that selects the sub-word line.
The first PMOS transistor P1 has a gate receiving the main word line signal MWLB, a source receiving the first sub-word line selection signal FX1, and a drain connected to an output line for outputting a signal that has been pulled up to the level of the first sub-word line selection signal FX1 as the first word line signal WL1.
The second to fourth word line drivers 120 to 140 have the same configurations as the first word line driver 110.
The first to fourth word line drivers 110 to 140 activate the first to fourth word line signals WL1 to WL4 in response to the main word line signal MWLB and the first to fourth sub-word line selection signals FX1 to FX4, respectively.
FIG. 2 is a layout diagram illustrating an arrangement of the PMOS transistor region 150 illustrated in FIG. 1.
Referring to FIG. 2, the PMOS transistor region 150 includes the first to fourth PMOS transistors (P1 to P4 of FIG. 1). The first to fourth PMOS transistors P1 to P4 include respective first to fourth active regions 210 to 240, a common gate region 250, and respective first to fourth metal lines M1 to M4.
The first to fourth active regions 210 to 240 are spaced apart from each other at specific intervals in a first direction D1.
Source regions SA are formed at both ends of each of the first to fourth active regions 210 to 240. Source contacts SC are formed in the source regions SA. The source contacts SC are connected to a metal line (not illustrated) and supplied with the first to fourth sub-word line selection signals (FX1 to FX4 of FIG. 1). The source contacts SC electrically connect the metal line (not illustrated) with the source regions SA.
Drain regions DA are formed in the first to fourth active regions 210 to 240 between the source regions SA formed at the both ends of each of the first to fourth active regions 210 to 240. First to fourth drain contacts DC1 to DC4 are formed in the drain regions DA formed in the first to fourth active regions 210 to 240, respectively.
The first to fourth drain contacts DC1 to DC4 are connected to the first to fourth metal lines M1 to M4 and supplied with the first to fourth word line signals (WL1 to WL4 of FIG. 1), respectively. The first to fourth metal lines M1 to M4 extend to a second direction D2, which is substantially perpendicular to the first direction D1, and are disposed to intersect the first to fourth active regions 210 to 240. The fourth metal line M4 is connected to the fourth drain contact DC4 formed in the fourth active region 240 and is electrically connected to the drain region DA of the fourth active region 240. The third metal line M3 is connected to the third drain contact DC3 formed in the third active region 230 and is electrically connected to the drain region DA of the third active region 230. The second metal line M2 is connected to the second drain contact DC2 formed in the second active region 220 and is electrically connected to the drain region DA of the second active region 220. The first metal line M1 is connected to the first drain contact DC1 formed in the first active region 210 and is electrically connected to the drain region DA of the first active region 210.
Each of the first to fourth metal lines M1 to M4 is configured to have the greatest width in an area where it is connected to each of the first to fourth drain contacts DC1 to DC4. Furthermore, each of the first to fourth metal lines M1 to M4 is configured to have a constant width in the remaining regions except for the area where it is connected to each of the first to fourth drain contacts DC1 to DC4.
The common gate region 250 is formed to surround the remaining regions except for the first to fourth drain contacts DC1 to DC4. The common gate region 250 includes four open parts OP. The open parts OP are formed by vertically penetrating the common gate region 250. The open parts OP are respectively configured to surround the first to fourth drain contacts DC1 to DC4 and to open the first to fourth drain contacts DC1 to DC4. The common gate region 250 is supplied with the main word line signal (MWLB of FIG. 1).
The first to fourth PMOS transistors P1 to P4 are driven in response to the first to fourth sub-word line selection signals FX1 to FX4 applied through the source contacts SC and the main word line signal MWLB applied through the common gate region 250. The first to fourth PMOS transistors P1 to P4 receive the respective first to fourth sub-word line selection signals FX1 to FX4 serving as pull-up driving signals selectively activated in response to the address information, through the source contacts SC. Accordingly, each of the first to fourth PMOS transistors P1 to P4 forms a current path between the corresponding source region and the corresponding drain region. The current path extends to the first to fourth metal lines M1 to M4 through the first to fourth drain contacts DC1 to DC4. The first to fourth word line signals WL1 to WL4 are activated due to the current path extended to the first to fourth metal lines M1 to M4.
More specifically, the second drain contact DC2 connected to the second metal line M2 and the third drain contact DC3 connected to the third metal line M3 are respectively formed in the centers of the metal lines M2 and M3 in the second direction D2 since the open parts OP of the common gate region 250 are formed to have the same pattern. In contrast, the first drain contact DC1 connected to the first metal line M1 and the fourth drain contact DC4 connected to the fourth metal line M4 are respectively inclined to sides of the metal lines M1 and M4 since the open parts OP of the common gate region 250 are formed to have the same size. Furthermore, the source contacts SC and the first to fourth drain contacts DC1 to DC4 formed in the first to fourth PMOS transistors P1 to P4 are not disposed in a line in the first direction D1. Accordingly, the intervals between the first to fourth drain contacts DC1 to DC4 and adjacent gate regions are not the same.
For example, assuming that the intervals between the first to fourth drain contacts DC1 to DC4 and one side of respective adjacent gate regions in the second direction D2 are A, B, C, and D and the intervals between the first to fourth drain contacts DC1 to DC4 and the other side of respective adjacent gate regions in the second direction D2 are A′, B′, C′, and D.′
The interval B and the interval B′ in the second transistor P2 are relatively the same. Likewise, the interval C and the interval C′ in the third transistor P3 are relatively the same. In contrast, the interval A and the interval A′ in the first PMOS transistor P1 are highly different. Likewise, the interval D and the interval D′ in the fourth PMOS transistor P4 are highly different.
Accordingly, the first to fourth PMOS transistors P1 to P4 have driving forces that are different from each other since the intervals between the drain contacts DC1 to DC4 and the common gate region 250 are not the same. That is, a difference in the intervals between the common gate region 250 supplied with the main word line signal MWLB and the first to fourth drain contacts DC1 to DC4 results in a difference in the parasitic capacitance between the adjacent gate regions and the drain region DA. Due to the difference in the parasitic capacitance, operating speed that activates the first word line signal WL1 and operating speed that activates the fourth word line signal WL4 are different.
Furthermore, leakage current is further increased as the interval between the common gate region 250 and the first to fourth drain contacts DC1 to DC4 is narrowed. The leakage current generated from the first PMOS transistor P1 and the fourth PMOS transistor P4 have influence on the first and fourth word line signals WL1 and WL4 generated through the first PMOS transistor P1 and the fourth PMOS transistor P4. Some of a plurality of memory cells connected to the first to fourth word lines are not normally driven in response to the first and fourth word line signals WL1 and WL4. As a result, an increase of the leakage current causes unwanted current consumption in the word line driver circuit including a plurality of transistors and deteriorates performance of the plurality of transistors.